The performance of an electronic integrated circuit may be measured with respect to different physical or logical characteristics, such as the propagation delay, power consumption, layout size, etc., or various combinations thereof. If it is a design goal to optimize the circuit with respect to a certain characteristic, for example, propagation delay, then the designer will make appropriate changes to the circuit parameters, such as increasing the transistor size in a relevant critical path, to achieve the goal. With each design change, new simulations are run to determine how much improvement was obtained, and to ensure that other aspects of the circuit are still within design constraints, for example, the increase in transistor size does not cause the circuit to draw an excessive amount of power.
It is known to optimize interrelated characteristics, such as these circuit aspects, using techniques are described in detail in: M. J. Box, "A New Method of Constrained Optimization and a Comparison With Other Methods," Computer Journal, Vol. 8, pp. 42-52, (1965), and Press et al., "Numerical Recipes in C," pp. 305-309 (Cambridge University Press 1988), both incorporated herein by reference.
However, these methods tend to be complex, and require significant amounts of computer time to run. Their results also must be closely scrutinized due to sensitivity of the methods to certain errors.
Accordingly, it is an object of the present invention to overcome the above described shortcomings, and to provide further improvements and advantages which will become apparent in view of the following disclosure.